circuit MYMAC :
  module MYMAC :
    input clock : Clock
    input reset : UInt<1>
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 65:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 65:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 65:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 66:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 66:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 66:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 67:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 67:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 68:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 68:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 68:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 69:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 69:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 69:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 70:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 70:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 70:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 70:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 70:27]

